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3.8.1
DSP Clock
The DSP is clocked at 8 MHz, with an effective 6 MHz operating frequency. The clock to the DSP is disabled for 1 clock prior
to each edge of the ΣΔ modulator clock to minimize noise during data conversion.
8 MHz OSC
6 MHz Digital
1MHz Modulator
Figure 13. Clock Generation
3.8.2
Decimation Sinc Filter
The serial data stream produced by the ΣΔ converter is decimated and converted to parallel values by a 3rd order 16:1 sinc
filter with a decimation factor of 8 or 16, depending on the Low Pass Filter selected.
H ( z ) = -----------------------------------
1 – z – 16
16 × ( 1 – z – 1 )
3
Figure 14. Sinc Filter Response, t S = 8 μ s
MMA655x
Sensor
Freescale Semiconductor, Inc.
25
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